// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  module_reg_offset.h
// Project line  :  IP
// Department    :  
// Author        :  Jason, Edward
// Version       :  .1
// Date          :  2011/11/29
// Description   :  The DDR PHY Controller Block
// Others        :  Generated automatically by nManager V4.2 
// History       :  Jason, Edward 2018/03/19 12:28:13 Create file
// ******************************************************************************

#ifndef __MODULE_REG_OFFSET_H__
#define __MODULE_REG_OFFSET_H__

/* module Base address of Module's Register */
#define PHY_Controller_module_BASE                       (0x0)

/******************************************************************************/
/*                      PHY_Controller module Registers' Definitions                            */
/******************************************************************************/

#define PHY_Controller_module_REVISION_REG         (PHY_Controller_module_BASE + 0x0)   /* This register shows current version of the PHY Control Block */
#define PHY_Controller_module_PHYINITCTRL_REG      (PHY_Controller_module_BASE + 0x4)   /* This register control the initialization of the PHY. Please note that write to this register will be ignored if init_en is already at '1' state. */
#define PHY_Controller_module_PHYINITSTATUS_REG    (PHY_Controller_module_BASE + 0x8)   /* This register shows the PHY status. */
#define PHY_Controller_module_PHYCLKGATED_REG      (PHY_Controller_module_BASE + 0xC)   /* This register control the clock gated of PHY */
#define PHY_Controller_module_PHYTIMER0_REG        (PHY_Controller_module_BASE + 0x10)  /* This register specified the timing parameter required by the PHY. */
#define PHY_Controller_module_PHYTIMER1_REG        (PHY_Controller_module_BASE + 0x14)  
#define PHY_Controller_module_PLLCTRL_REG          (PHY_Controller_module_BASE + 0x18)  /* This register specified the timing paramters for PLL in both address /command, and data block. */
#define PHY_Controller_module_PLLTIMER_REG         (PHY_Controller_module_BASE + 0x1C)  /* This register specified the control for PLL in both address /command, and data block. */
#define PHY_Controller_module_DLYMEASCTRL_REG      (PHY_Controller_module_BASE + 0x20)  /* This register specify the control for delay measurement of the read delay line. */
#define PHY_Controller_module_IMPCTRL_REG          (PHY_Controller_module_BASE + 0x24)  /* This register specify the control the ZQ calibration. */
#define PHY_Controller_module_IMPSTATUS_REG        (PHY_Controller_module_BASE + 0x28)  /* This register specify the ZQ calibration result. */
#define PHY_Controller_module_DRAMCFG_REG          (PHY_Controller_module_BASE + 0x2C)  /* This register is used to configure the DRAM system. */
#define PHY_Controller_module_DRAMTIMER0_REG       (PHY_Controller_module_BASE + 0x30)  /* This register specify the DRAM timing parameters. Please note that the command delay specified in this register only apply to command issued by the PHY controller internally. */
#define PHY_Controller_module_DRAMTIMER1_REG       (PHY_Controller_module_BASE + 0x34)  /* This register specify the DRAM timing parameters. Please note that the command delay specified in this register only apply to command issued by the PHY controller internally. */
#define PHY_Controller_module_DRAMTIMER2_REG       (PHY_Controller_module_BASE + 0x38)  /* This register specify the DRAM timing parameters. Please note that the command delay specified in this register only apply to command issued by the PHY controller internally. */
#define PHY_Controller_module_DRAMTIMER3_REG       (PHY_Controller_module_BASE + 0x3C)  /* This register specify the DRAM timing parameters. Please note that the command delay specified in this register only apply to command issued by the PHY controller internally. */
#define PHY_Controller_module_DRAMTIMER4_REG       (PHY_Controller_module_BASE + 0x40)  /* This register specify the DRAM Write Leveling timing parameter. This register only applied to DDR3/LPDDR3 type SDRAM. */
#define PHY_Controller_module_ODTCR_REG            (PHY_Controller_module_BASE + 0x44)  /* This register specify the ODT control on different rank while reading or writing to particular rank. */
#define PHY_Controller_module_TRAINCTRL0_REG       (PHY_Controller_module_BASE + 0x48)  /* This register specify the training control. */
#define PHY_Controller_module_RANKEN_REG           (PHY_Controller_module_BASE + 0x4C)  /* This register specify the training rank control. */
#define PHY_Controller_module_TRAINMADDR_REG       (PHY_Controller_module_BASE + 0x50)  /* This register specify the starting memory address where can be used to do data training. The minimum space required for data training should be 64-bytes, and the allocated memory should be 64-bytes alignment. */
#define PHY_Controller_module_BISTCTRL_REG         (PHY_Controller_module_BASE + 0x54)  /* This register specify the behavior of the built-in self test. */
#define PHY_Controller_module_BISTDATA0_REG        (PHY_Controller_module_BASE + 0x58)  /* This register specify the BIST data used for DRAM loopback test. Please note that this register only valid while the bist_pat is set to "User Defined" */
#define PHY_Controller_module_BISTDATA1_REG        (PHY_Controller_module_BASE + 0x5C)  
#define PHY_Controller_module_BISTSTATUS_REG       (PHY_Controller_module_BASE + 0x60)  /* This register shows the result and status of BIST testing. */
#define PHY_Controller_module_MODEREG01_REG        (PHY_Controller_module_BASE + 0x64)  /* This register defines the contents of the Mode Register. */
#define PHY_Controller_module_MODEREG23_REG        (PHY_Controller_module_BASE + 0x68)  /* This register defines the contents of the Mode Register. */
#define PHY_Controller_module_DETPATTERN_REG       (PHY_Controller_module_BASE + 0x6C)  /* Write/Read DET Pattern Register.These fields are used to fine-tune the training procedure. Users are not recommend to modify them. */
#define PHY_Controller_module_MISC_REG             (PHY_Controller_module_BASE + 0x70)  /* Miscellaneous control register */
#define PHY_Controller_module_RNK2RNK_REG          (PHY_Controller_module_BASE + 0x74)  /* Rank to rank delay control register */
#define PHY_Controller_module_PHYCTRL0_REG         (PHY_Controller_module_BASE + 0x78)  /* PHY control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_module_PHYDBG_REG           (PHY_Controller_module_BASE + 0x7C)  /* PHY debug registers */
#define PHY_Controller_module_RETCTRL0_REG         (PHY_Controller_module_BASE + 0x80)  /* ReTrain Control */
#define PHY_Controller_module_DMSEL_REG            (PHY_Controller_module_BASE + 0x84)  /* DM Swap Selection */
#define PHY_Controller_module_TRAINCTRL8_REG       (PHY_Controller_module_BASE + 0x88)  /* This register control the data training. */
#define PHY_Controller_module_DQSSEL_REG           (PHY_Controller_module_BASE + 0x8C)  /* Swap of DQ in PHY */
#define PHY_Controller_module_TRAINCTRL9_REG       (PHY_Controller_module_BASE + 0x90)  /* This register control the data training. */
#define PHY_Controller_module_TRAINCTRL10_REG      (PHY_Controller_module_BASE + 0x94)  /* This register specify the training control. */
#define PHY_Controller_module_PHYPLLCTRL_AC_REG    (PHY_Controller_module_BASE + 0x98)  /* PHY PLL control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_module_PHYPLLCTRL_DX_REG    (PHY_Controller_module_BASE + 0x9C)  /* PHY PLL control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_module_SWTMODE_REG          (PHY_Controller_module_BASE + 0xA0)  /* This register is for setting S/W training mode */
#define PHY_Controller_module_SWTWLDQS_REG         (PHY_Controller_module_BASE + 0xA4)  /* This register is for issuing write DQS in S/W write leveling training */
#define PHY_Controller_module_SWTRLT_REG           (PHY_Controller_module_BASE + 0xA8)  /* S/W training result */
#define PHY_Controller_module_PHYRSCTRL_REG        (PHY_Controller_module_BASE + 0xB0)  /* PHY Register Slice Contrl */
#define PHY_Controller_module_BISTCTRL2_REG        (PHY_Controller_module_BASE + 0xB4)  /* BISTCTRL2 */
#define PHY_Controller_module_TRAINMADDRTG1_REG    (PHY_Controller_module_BASE + 0xB8)  /* This register specify the starting memory address where can be used to do data training. The minimum space required for data training should be 64-bytes, and the allocated memory should be 64-bytes alignment. */
#define PHY_Controller_module_DRAMTIMER5_REG       (PHY_Controller_module_BASE + 0xBC)  
#define PHY_Controller_module_VREFTCTRL_REG        (PHY_Controller_module_BASE + 0xC0)  /* VREF Training Control Register.This register specify the common settings of the VREF training. */
#define PHY_Controller_module_DVRFTCTRL_REG        (PHY_Controller_module_BASE + 0xC4)  /* DRAM VREF Training Control Regiser.Register in this field are used to controls the behavior of the VREF training. */
#define PHY_Controller_module_HVRFTCTRL_REG        (PHY_Controller_module_BASE + 0xC8)  /* Host VREF Training Control Regiser.Register in this field are used to controls the behavior of the Host VREF training. */
#define PHY_Controller_module_TRAINCTRL1_REG       (PHY_Controller_module_BASE + 0xD0)  /* This register control the data training. */
#define PHY_Controller_module_TRAINCTRL2_REG       (PHY_Controller_module_BASE + 0xD4)  /* This register control the data training. */
#define PHY_Controller_module_REGBANKCTRL_REG      (PHY_Controller_module_BASE + 0xD8)  /* This register control the register bank. */
#define PHY_Controller_module_TRAINCTRL3_REG       (PHY_Controller_module_BASE + 0xDC)  /* This register control the data training. */
#define PHY_Controller_module_MODEREG45_REG        (PHY_Controller_module_BASE + 0xE0)  /* This register defines the contents of the Mode Register. */
#define PHY_Controller_module_MODEREG67_REG        (PHY_Controller_module_BASE + 0xE4)  /* This register defines the contents of the Mode Register. */
#define PHY_Controller_module_TRAINCTRL6_REG       (PHY_Controller_module_BASE + 0xE8)  /* This register control the data training. */
#define PHY_Controller_module_DETPATINDEX_REG      (PHY_Controller_module_BASE + 0xEC)  /* Write/Read DET Pattern INDEX Register.These fields are used to select the related DETPATTERN. Users are not recommend to modify them. */
#define PHY_Controller_module_TRAINSTEP0_REG       (PHY_Controller_module_BASE + 0xF4)  /* This register control the data training step. */
#define PHY_Controller_module_TRAINSTEP1_REG       (PHY_Controller_module_BASE + 0xF8)  /* This register control the data training step. */
#define PHY_Controller_module_TRAINSTEP2_REG       (PHY_Controller_module_BASE + 0xFC)  /* This register control the data training step. */
#define PHY_Controller_module_ACBISTCTRL0_REG      (PHY_Controller_module_BASE + 0x100) /* This register control the comparison while BIST activated. */
#define PHY_Controller_module_ACBISTCTRL1_REG      (PHY_Controller_module_BASE + 0x104) /* This register control the comparison while BIST activated. */
#define PHY_Controller_module_ACBISTSTS0_REG       (PHY_Controller_module_BASE + 0x108) /* This register shows the results and status of the BIST test. Please note that this register is read-only, and can only be reset by bist_op setting to BIST Reset. */
#define PHY_Controller_module_ACBISTSTS1_REG       (PHY_Controller_module_BASE + 0x10C) /* This register shows the results and status of the BIST test. Please note that this register is read-only, and can only be reset by bist_op setting to BIST Reset. */
#define PHY_Controller_module_WDXBOUND_DFS_REG     (PHY_Controller_module_BASE + 0x110) /* This register indicate the wdet lb roundary. */
#define PHY_Controller_module_TRAINCTRL4_REG       (PHY_Controller_module_BASE + 0x114) /* This register control the data training. */
#define PHY_Controller_module_TRAINCTRL5_REG       (PHY_Controller_module_BASE + 0x118) /* This register control the data training. */
#define PHY_Controller_module_TRAINCTRL7_REG       (PHY_Controller_module_BASE + 0x11C) /* This register control the data training. */
#define PHY_Controller_module_ACCMDBDL0_REG        (PHY_Controller_module_BASE + 0x120) /* CA Training cmd1t phase boundary */
#define PHY_Controller_module_IMPOFFSET_REG        (PHY_Controller_module_BASE + 0x124) /* ZQCAL offset control */
#define PHY_Controller_module_ACCMDBDL2_REG        (PHY_Controller_module_BASE + 0x128) /* AC command bit delay line setting */
#define PHY_Controller_module_ACCMDBDL3_REG        (PHY_Controller_module_BASE + 0x12C) /* Reserved */
#define PHY_Controller_module_ACCMDBDL5_REG        (PHY_Controller_module_BASE + 0x134) /* Reserved */
#define PHY_Controller_module_ACCMDBDL6_REG        (PHY_Controller_module_BASE + 0x138) /* AC command bit delay line setting */
#define PHY_Controller_module_ACCMDBDL7_REG        (PHY_Controller_module_BASE + 0x13C) /* AC command bit delay line setting */
#define PHY_Controller_module_ACADDRBDL0_REG       (PHY_Controller_module_BASE + 0x140) /* AC address bit delay line setting */
#define PHY_Controller_module_ACADDRBDL1_REG       (PHY_Controller_module_BASE + 0x144) /* AC address bit delay line setting */
#define PHY_Controller_module_ACADDRBDL2_REG       (PHY_Controller_module_BASE + 0x148) /* AC address bit delay line setting */
#define PHY_Controller_module_ACADDRBDL3_REG       (PHY_Controller_module_BASE + 0x14C) /* AC address bit delay line setting */
#define PHY_Controller_module_ACADDRBDL4_REG       (PHY_Controller_module_BASE + 0x150) /* AC address bit delay line setting */
#define PHY_Controller_module_ACADDRBDL5_REG       (PHY_Controller_module_BASE + 0x154) /* AC address bit delay line setting */
#define PHY_Controller_module_ACADDRBDL6_REG       (PHY_Controller_module_BASE + 0x158) /* AC address bit delay line setting */
#define PHY_Controller_module_ACADDRBDL7_REG       (PHY_Controller_module_BASE + 0x15C) /* AC address bit delay line setting */
#define PHY_Controller_module_ACADDRBDL8_REG       (PHY_Controller_module_BASE + 0x160) /* AC address bit delay line setting */
#define PHY_Controller_module_ACADDRBDL9_REG       (PHY_Controller_module_BASE + 0x164) /* AC address bit delay line setting */
#define PHY_Controller_module_ACBISTCTRL2_REG      (PHY_Controller_module_BASE + 0x168) /* This register control the comparison while BIST activated. */
#define PHY_Controller_module_PLLJTMT_REG          (PHY_Controller_module_BASE + 0x16C) /* PLL jitter metter control register and status */
#define PHY_Controller_module_IMP_CTRL1_REG        (PHY_Controller_module_BASE + 0x170) /* AC/DX ZQ selection */
#define PHY_Controller_module_IMP_STATUS1_REG      (PHY_Controller_module_BASE + 0x174) /* AC ZCAL status */
#define PHY_Controller_module_IMP_OUT_REG          (PHY_Controller_module_BASE + 0x178) /* IMP CAL output value */
#define PHY_Controller_module_TRAINCTRL11_REG      (PHY_Controller_module_BASE + 0x17C) /* This register control the data training. */
#define PHY_Controller_module_FASTGDSRESULT0_REG   (PHY_Controller_module_BASE + 0x180) /* Fast gate trainning and fast GDS trainning result that can be read by users */
#define PHY_Controller_module_FASTGDSRESULT1_REG   (PHY_Controller_module_BASE + 0x184) /* Fast gate trainning and fast GDS trainning result that can be read by users */
#define PHY_Controller_module_FASTGTRESULT_REG     (PHY_Controller_module_BASE + 0x188) /* Fast gate trainning and fast GDS trainning result that can be read by users */
#define PHY_Controller_module_TRKDBG_REG           (PHY_Controller_module_BASE + 0x18C) /* DQS/DQSG Dynamic Tracking information for debug */
#define PHY_Controller_module_PACKDEBUG_REG        (PHY_Controller_module_BASE + 0x190) /* PACK debug signals */
#define PHY_Controller_module_ACPHYRSVDC_REG       (PHY_Controller_module_BASE + 0x194) /* AC block PHY reserved control pins. This register is for PHY control and should not be modified. */
#define PHY_Controller_module_ACPHYRSVDS_REG       (PHY_Controller_module_BASE + 0x198) /* AC block PHY reserved control pins. This register is for PHY control and should not be modified. */
#define PHY_Controller_module_SWMRRDATA_REG        (PHY_Controller_module_BASE + 0x19C) /* SW MRR data for read. */
#define PHY_Controller_module_ACCMDBDL8_REG        (PHY_Controller_module_BASE + 0x1A0) /* AC command bit delay line setting */
#define PHY_Controller_module_ACCMDBDL9_REG        (PHY_Controller_module_BASE + 0x1A4) /* AC command bit delay line setting */
#define PHY_Controller_module_ACCMDBDL10_REG       (PHY_Controller_module_BASE + 0x1A8) /* AC command bit delay line setting */
#define PHY_Controller_module_ACCMDBDL11_REG       (PHY_Controller_module_BASE + 0x1AC) /* AC command bit delay line setting */
#define PHY_Controller_module_CATBDLBOUNDSEL_REG   (PHY_Controller_module_BASE + 0x1B0) /* CA Training addr bdl boundary selection */
#define PHY_Controller_module_CATBDLBOUND_REG      (PHY_Controller_module_BASE + 0x1B4) /* CA Training addr bdl boundary */
#define PHY_Controller_module_CATSWAPINDEX_REG     (PHY_Controller_module_BASE + 0x1B8) /* CA SWAP index register */
#define PHY_Controller_module_CATSWAPSEL_REG       (PHY_Controller_module_BASE + 0x1BC) /* CA SWAP select register, indexed by CATSWAPINDEX */
#define PHY_Controller_module_CATTIMER0_REG        (PHY_Controller_module_BASE + 0x1C0) /* CA Training Timer0 */
#define PHY_Controller_module_CATTIMER1_REG        (PHY_Controller_module_BASE + 0x1C4) /* CA Training Timer1 */
#define PHY_Controller_module_CATCONFIG_REG        (PHY_Controller_module_BASE + 0x1C8) /* CA Training Configuration */
#define PHY_Controller_module_CATRESULT_REG        (PHY_Controller_module_BASE + 0x1CC) /* CA Training result for debug */
#define PHY_Controller_module_PHYDQRESULT_REG      (PHY_Controller_module_BASE + 0x1D0) /* SW CA Training DQ result from PHY */
#define PHY_Controller_module_ADDRPHBOUND_REG      (PHY_Controller_module_BASE + 0x1D4) /* CA Training addr phase boundary */
#define PHY_Controller_module_SWCATPATTERN_P_REG   (PHY_Controller_module_BASE + 0x1D8) /* SW CA Training pattern for  positive CK edge */
#define PHY_Controller_module_PACKDEBUG1_REG       (PHY_Controller_module_BASE + 0x1DC) /* PACK debug signals */
#define PHY_Controller_module_MRS_SEQ_PROG_REG     (PHY_Controller_module_BASE + 0x1E0) /* Programmed MRS sequence in the DRAM initialization */
#define PHY_Controller_module_LPCTRL_REG           (PHY_Controller_module_BASE + 0x1E4) /* Low Power Control Register */
#define PHY_Controller_module_TRAINCTRL12_REG      (PHY_Controller_module_BASE + 0x1E8) /* TRAINCTRL 12 Register */
#define PHY_Controller_module_CATCONFIG1_REG       (PHY_Controller_module_BASE + 0x1EC) /* CA Training Configuration */
#define PHY_Controller_module_AHVREFT_STATUS_REG   (PHY_Controller_module_BASE + 0x1F0) /* Host PHY VREF(AC) Training Result. This register shows the training result of the Host PHY VREF(AC) training.This register is only valid while the application is LPDDR4. */
#define PHY_Controller_module_ADVREF_STATUS_REG    (PHY_Controller_module_BASE + 0x1F4) /* DRAM VREF(AC) Training Result. This register shows the training result of the DRAM VREF(DQ) training.This register is only valid while the application is LPDDR4. */
#define PHY_Controller_module_DLYMEASCTRL1_REG     (PHY_Controller_module_BASE + 0x1F8) /* DQ, DQS and DQSG Dynamic Tracking Register */
#define PHY_Controller_module_DFIMISCCTRL_REG      (PHY_Controller_module_BASE + 0x1FC) /* DFI MISC control register */
#define PHY_Controller_module_DXNBISTCTRL_0_REG    (PHY_Controller_module_BASE + 0x200) /* This register is used to control if the loopback data is compre during BIST of Data Blocks. */
#define PHY_Controller_module_DXNBISTCTRL_1_REG    (PHY_Controller_module_BASE + 0x280) /* This register is used to control if the loopback data is compre during BIST of Data Blocks. */
#define PHY_Controller_module_DXNBISTSTS_0_REG     (PHY_Controller_module_BASE + 0x204) /* This register shows the results and status of the BIST test. Please note that this register is read-only, and can only be reset by bist_op setting to BIST Reset. */
#define PHY_Controller_module_DXNBISTSTS_1_REG     (PHY_Controller_module_BASE + 0x284) /* This register shows the results and status of the BIST test. Please note that this register is read-only, and can only be reset by bist_op setting to BIST Reset. */
#define PHY_Controller_module_DXNCTRL_0_REG        (PHY_Controller_module_BASE + 0x208) /* This register is used to control Data Block */
#define PHY_Controller_module_DXNCTRL_1_REG        (PHY_Controller_module_BASE + 0x288) /* This register is used to control Data Block */
#define PHY_Controller_module_DXNWDQNBDL0_0_REG    (PHY_Controller_module_BASE + 0x210) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNWDQNBDL0_1_REG    (PHY_Controller_module_BASE + 0x290) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNWDQNBDL0_2_REG    (PHY_Controller_module_BASE + 0x610) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNWDQNBDL0_3_REG    (PHY_Controller_module_BASE + 0x690) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNWDQNBDL1_0_REG    (PHY_Controller_module_BASE + 0x214) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNWDQNBDL1_1_REG    (PHY_Controller_module_BASE + 0x294) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNWDQNBDL1_2_REG    (PHY_Controller_module_BASE + 0x614) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNWDQNBDL1_3_REG    (PHY_Controller_module_BASE + 0x694) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNWDQNBDL2_0_REG    (PHY_Controller_module_BASE + 0x218) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNWDQNBDL2_1_REG    (PHY_Controller_module_BASE + 0x298) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNWDQNBDL2_2_REG    (PHY_Controller_module_BASE + 0x618) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNWDQNBDL2_3_REG    (PHY_Controller_module_BASE + 0x698) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL0_0_REG    (PHY_Controller_module_BASE + 0x21C) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL0_1_REG    (PHY_Controller_module_BASE + 0x29C) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL0_2_REG    (PHY_Controller_module_BASE + 0x61C) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL0_3_REG    (PHY_Controller_module_BASE + 0x69C) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL0_4_REG    (PHY_Controller_module_BASE + 0xA1C) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL0_5_REG    (PHY_Controller_module_BASE + 0xA9C) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL0_6_REG    (PHY_Controller_module_BASE + 0xE1C) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL0_7_REG    (PHY_Controller_module_BASE + 0xE9C) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL1_0_REG    (PHY_Controller_module_BASE + 0x220) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL1_1_REG    (PHY_Controller_module_BASE + 0x2A0) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL1_2_REG    (PHY_Controller_module_BASE + 0x620) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL1_3_REG    (PHY_Controller_module_BASE + 0x6A0) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL1_4_REG    (PHY_Controller_module_BASE + 0xA20) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL1_5_REG    (PHY_Controller_module_BASE + 0xAA0) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL1_6_REG    (PHY_Controller_module_BASE + 0xE20) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL1_7_REG    (PHY_Controller_module_BASE + 0xEA0) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL2_0_REG    (PHY_Controller_module_BASE + 0x224) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL2_1_REG    (PHY_Controller_module_BASE + 0x2A4) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL2_2_REG    (PHY_Controller_module_BASE + 0x624) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL2_3_REG    (PHY_Controller_module_BASE + 0x6A4) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL2_4_REG    (PHY_Controller_module_BASE + 0xA24) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL2_5_REG    (PHY_Controller_module_BASE + 0xAA4) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL2_6_REG    (PHY_Controller_module_BASE + 0xE24) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNRDQNBDL2_7_REG    (PHY_Controller_module_BASE + 0xEA4) /* This register is used to control the bit delay line of the DATA block. */
#define PHY_Controller_module_DXNOEBDL_0_REG       (PHY_Controller_module_BASE + 0x228) /* Output Enable Delay Line Control. This register specify the dely line value of the output enable delay line within PHY data block. */
#define PHY_Controller_module_DXNOEBDL_1_REG       (PHY_Controller_module_BASE + 0x2A8) /* Output Enable Delay Line Control. This register specify the dely line value of the output enable delay line within PHY data block. */
#define PHY_Controller_module_DXNOEBDL_2_REG       (PHY_Controller_module_BASE + 0x628) /* Output Enable Delay Line Control. This register specify the dely line value of the output enable delay line within PHY data block. */
#define PHY_Controller_module_DXNOEBDL_3_REG       (PHY_Controller_module_BASE + 0x6A8) /* Output Enable Delay Line Control. This register specify the dely line value of the output enable delay line within PHY data block. */
#define PHY_Controller_module_DXNRDQSDLY_0_REG     (PHY_Controller_module_BASE + 0x22C) /* This register is used to control the local delay line. */
#define PHY_Controller_module_DXNRDQSDLY_1_REG     (PHY_Controller_module_BASE + 0x2AC) /* This register is used to control the local delay line. */
#define PHY_Controller_module_DXNWDQSDLY_0_REG     (PHY_Controller_module_BASE + 0x230) /* This register is used to control the write leveling DQS delays. */
#define PHY_Controller_module_DXNWDQSDLY_1_REG     (PHY_Controller_module_BASE + 0x2B0) /* This register is used to control the write leveling DQS delays. */
#define PHY_Controller_module_DXNWDQSDLY_2_REG     (PHY_Controller_module_BASE + 0x630) /* This register is used to control the write leveling DQS delays. */
#define PHY_Controller_module_DXNWDQSDLY_3_REG     (PHY_Controller_module_BASE + 0x6B0) /* This register is used to control the write leveling DQS delays. */
#define PHY_Controller_module_DXNWDQDLY_0_REG      (PHY_Controller_module_BASE + 0x234) /* This register is used to control the write leveling delay line. */
#define PHY_Controller_module_DXNWDQDLY_1_REG      (PHY_Controller_module_BASE + 0x2B4) /* This register is used to control the write leveling delay line. */
#define PHY_Controller_module_DXNWDQDLY_2_REG      (PHY_Controller_module_BASE + 0x634) /* This register is used to control the write leveling delay line. */
#define PHY_Controller_module_DXNWDQDLY_3_REG      (PHY_Controller_module_BASE + 0x6B4) /* This register is used to control the write leveling delay line. */
#define PHY_Controller_module_DXNWLSL_0_REG        (PHY_Controller_module_BASE + 0x238) /* This reister is used to control if PHY controller add extra system latency. */
#define PHY_Controller_module_DXNWLSL_1_REG        (PHY_Controller_module_BASE + 0x2B8) /* This reister is used to control if PHY controller add extra system latency. */
#define PHY_Controller_module_DXNWLSL_2_REG        (PHY_Controller_module_BASE + 0x638) /* This reister is used to control if PHY controller add extra system latency. */
#define PHY_Controller_module_DXNWLSL_3_REG        (PHY_Controller_module_BASE + 0x6B8) /* This reister is used to control if PHY controller add extra system latency. */
#define PHY_Controller_module_DXNGDS_0_REG         (PHY_Controller_module_BASE + 0x23C) /* This register is used to control the latch enable within the PHY to get the stable data. */
#define PHY_Controller_module_DXNGDS_1_REG         (PHY_Controller_module_BASE + 0x2BC) /* This register is used to control the latch enable within the PHY to get the stable data. */
#define PHY_Controller_module_DXNGDS_2_REG         (PHY_Controller_module_BASE + 0x63C) /* This register is used to control the latch enable within the PHY to get the stable data. */
#define PHY_Controller_module_DXNGDS_3_REG         (PHY_Controller_module_BASE + 0x6BC) /* This register is used to control the latch enable within the PHY to get the stable data. */
#define PHY_Controller_module_DXNRDQSGDLY_0_REG    (PHY_Controller_module_BASE + 0x240) /* This register is used to control the local delay line. */
#define PHY_Controller_module_DXNRDQSGDLY_1_REG    (PHY_Controller_module_BASE + 0x2C0) /* This register is used to control the local delay line. */
#define PHY_Controller_module_DXNRDQSGDLY_2_REG    (PHY_Controller_module_BASE + 0x640) /* This register is used to control the local delay line. */
#define PHY_Controller_module_DXNRDQSGDLY_3_REG    (PHY_Controller_module_BASE + 0x6C0) /* This register is used to control the local delay line. */
#define PHY_Controller_module_DXNWDQNLB0_0_REG     (PHY_Controller_module_BASE + 0x244) /* This register is used to latch the WDQ left boundary of current rank after WDET */
#define PHY_Controller_module_DXNWDQNLB0_1_REG     (PHY_Controller_module_BASE + 0x2C4) /* This register is used to latch the WDQ left boundary of current rank after WDET */
#define PHY_Controller_module_DXNRDQSDLYSUB_0_REG  (PHY_Controller_module_BASE + 0x248) /* This register is used to control the local delay line. */
#define PHY_Controller_module_DXNRDQSDLYSUB_1_REG  (PHY_Controller_module_BASE + 0x2C8) /* This register is used to control the local delay line. */
#define PHY_Controller_module_DXNRDBOUND_0_REG     (PHY_Controller_module_BASE + 0x250) /* Read data eye boundary. This register indicates the left/right boundary of RDQSQDL of the data eye. */
#define PHY_Controller_module_DXNRDBOUND_1_REG     (PHY_Controller_module_BASE + 0x2D0) /* Read data eye boundary. This register indicates the left/right boundary of RDQSQDL of the data eye. */
#define PHY_Controller_module_DXNWRBOUND_0_REG     (PHY_Controller_module_BASE + 0x254) /* Write data eye boundary. This register indicates the left/right boundary of WDQSQDL of the data eye. */
#define PHY_Controller_module_DXNWRBOUND_1_REG     (PHY_Controller_module_BASE + 0x2D4) /* Write data eye boundary. This register indicates the left/right boundary of WDQSQDL of the data eye. */
#define PHY_Controller_module_DXNWDQNLB1_0_REG     (PHY_Controller_module_BASE + 0x25C) /* This register is used to latch the WDQ left boundary of current rank after WDET */
#define PHY_Controller_module_DXNWDQNLB1_1_REG     (PHY_Controller_module_BASE + 0x2DC) /* This register is used to latch the WDQ left boundary of current rank after WDET */
#define PHY_Controller_module_DXDEBUG0_0_REG       (PHY_Controller_module_BASE + 0x268) /* Data block PHY debug signals */
#define PHY_Controller_module_DXDEBUG0_1_REG       (PHY_Controller_module_BASE + 0x2E8) /* Data block PHY debug signals */
#define PHY_Controller_module_DXDEBUG1_0_REG       (PHY_Controller_module_BASE + 0x26C) /* Data block PHY debug signals */
#define PHY_Controller_module_DXDEBUG1_1_REG       (PHY_Controller_module_BASE + 0x2EC) /* Data block PHY debug signals */
#define PHY_Controller_module_DVREFT_STATUS_0_REG  (PHY_Controller_module_BASE + 0x270) /* DRAM VREF(DQ) Training Result. This register shows the training result of the DRAM VREF(DQ) training. */
#define PHY_Controller_module_DVREFT_STATUS_1_REG  (PHY_Controller_module_BASE + 0x2F0) /* DRAM VREF(DQ) Training Result. This register shows the training result of the DRAM VREF(DQ) training. */
#define PHY_Controller_module_HVREFT_STATUS_0_REG  (PHY_Controller_module_BASE + 0x274) /* Host PHY VREF(DQ) Training Result. This register shows the training result of the Host PHY VREF(DQ) training. */
#define PHY_Controller_module_HVREFT_STATUS_1_REG  (PHY_Controller_module_BASE + 0x2F4) /* Host PHY VREF(DQ) Training Result. This register shows the training result of the Host PHY VREF(DQ) training. */
#define PHY_Controller_module_HVREFT_STATUS_2_REG  (PHY_Controller_module_BASE + 0x674) /* Host PHY VREF(DQ) Training Result. This register shows the training result of the Host PHY VREF(DQ) training. */
#define PHY_Controller_module_HVREFT_STATUS_3_REG  (PHY_Controller_module_BASE + 0x6F4) /* Host PHY VREF(DQ) Training Result. This register shows the training result of the Host PHY VREF(DQ) training. */
#define PHY_Controller_module_DXNTRACKSTATUS_0_REG (PHY_Controller_module_BASE + 0x278) /* This register is used to record dm and dq overflow/underflow status . */
#define PHY_Controller_module_DXNTRACKSTATUS_1_REG (PHY_Controller_module_BASE + 0x2F8) /* This register is used to record dm and dq overflow/underflow status . */
#define PHY_Controller_module_DXNTRACKSTATUS_2_REG (PHY_Controller_module_BASE + 0x678) /* This register is used to record dm and dq overflow/underflow status . */
#define PHY_Controller_module_DXNTRACKSTATUS_3_REG (PHY_Controller_module_BASE + 0x6F8) /* This register is used to record dm and dq overflow/underflow status . */
#define PHY_Controller_module_DXNTRACKSTATUS_4_REG (PHY_Controller_module_BASE + 0xA78) /* This register is used to record dm and dq overflow/underflow status . */
#define PHY_Controller_module_DXNTRACKSTATUS_5_REG (PHY_Controller_module_BASE + 0xAF8) /* This register is used to record dm and dq overflow/underflow status . */
#define PHY_Controller_module_DXNTRACKSTATUS_6_REG (PHY_Controller_module_BASE + 0xE78) /* This register is used to record dm and dq overflow/underflow status . */
#define PHY_Controller_module_DXNTRACKSTATUS_7_REG (PHY_Controller_module_BASE + 0xEF8) /* This register is used to record dm and dq overflow/underflow status . */
#define PHY_Controller_module_VREFT_BOUND_0_REG    (PHY_Controller_module_BASE + 0x27C) /* VREF Training LB & RB Result. */
#define PHY_Controller_module_VREFT_BOUND_1_REG    (PHY_Controller_module_BASE + 0x2FC) /* VREF Training LB & RB Result. */
#define PHY_Controller_module_PLLSTATUS_REG        (PHY_Controller_module_BASE + 0xAC)  /* PLL Unlock Error Status */
#define PHY_Controller_module_BISTCTRL1_REG        (PHY_Controller_module_BASE + 0xF0)  /* BISTCTRL1 */
#define PHY_Controller_module_DETPATTERN1_REG      (PHY_Controller_module_BASE + 0xCC)  /* Write/Read DET Pattern Register.These fields are used to generate the DET pattern  that like MR45. */
#define PHY_Controller_module_APB_WR_MASK_INFO_REG (PHY_Controller_module_BASE + 0x130) /* when the Register Write Protection Mode is enabled,these fields record the first error address and count error number. */

#endif // __MODULE_REG_OFFSET_H__
